Silicon-on-insulator (SOI) wafer is a starting material for manufacturing semiconductor devices and integrated circuits. SOI wafers are the starting material that replaces bulk silicon wafers in high-speed, low power, radiation-hard, high-level integration, and others high-end areas of semiconductor chip manufacturing.
There are several methods that are currently in use for manufacturing of the SOI wafer:    (1) separation by implanted oxygen (SIMOX), described by Izumi et al. in 1978 (K. Izumi, M. Doken and H. Ariyoshi, Electron Letters 14, 1978, p. 593)    (2) bond-and-ethchback silicon-on-insulator (BESOI) described by Lasky in 1986 (J. B. Lasky, “Wafer bonding for silicon-on-insulator technologies” Appl. Phys. Lett. Vol. 48, p. 76, 1986)    (3) layer transfer (Smart-Cut) described by Bruel in 1992 (U.S. Pat. No. 5,374,564).
The most advanced method is the layer transfer. The layer transfer method consists from the following steps as it schematically shown on FIG. 1:    (1) providing a donor wafer 101    (2) forming a fragile plane layer 102 for separation inside of the donor wafer 101 thus defining a cap layer 111    (3) providing a handle wafer 103; the handle wafer 103 typically comprises a silicon wafer with an insulator (i.e., silicon dioxide) layer 104; alternatively, the donor wafer is oxidized and thus covered with the layer 104, or both wafer 101 and wafer 103 have the insulator layer 104 on their surfaces    (3) initial attaching of said donor wafer 101 to said handle wafer 103 along an interface 105 thus making a temporary wafer assembly 106    (4) separation of said assembly 106 along said fragile plane 102; this step might include a substep of additional fragilization of said plane 102. An SOI wafer 107 and a leftover wafer 108 are formed upon the separation step. A layer 111 can be now considered as a layer transferred from the wafer 101 to the wafer 103, thus giving a name to the method. Said SOI wafer 107 consists from a handle 109, buried oxide layer 104, cap layer 111 with working surface 112    (5) finalizing of the SOI wafer 107 that includes strengthening of initial attachment along the interface 105, perfecting of crystalline quality of the cap layer 111, smoothing of said working surface 112. The finalizing step might also include shaping of SOI wafer edges, thinning of the cap layer 111, surface polishing, and other optional operations.
Several versions of the layer transfer method are known in the prior art. The versions comprises different ways to form the fragile layer 102, different ways of separation of the assembly 106, etc. For example, separation can be thermally induced (Bruel, U.S. Pat. No. 5,374,564), water jet induced (K. Sakaguchi, K. Yanagita, H. Kurisu, H. Suzuki, K. Ohmi, T. Yonehara, ELTRAN by water-jet splitting in stress-controlled porous Si, IEEE International SOI Conference, Oct. 4–Oct. 7, 1999, Rohnert Park, Calif., USA, p. 110–111), bend induced (Usenko, U.S. Pat. No. 6,352,909), and via blade insertion (K. Henttinen, T. Suni, A. Nurmela, I. Suni, S. S. Lau, T. Höchbauer, M. Nastasi and V. -M. Airaksinen, “Cold ion-cutting of hydrogen implanted Si”, Nuclear Instr. and Meth. in Phys. Research B, Vol. 190, May 2002, Pages 761–766.).
However, separation techniques and other late process stages are dependent on the earlier more fundamental stage of forming of the fragile plane layer 102. The fragilization process determines the thickness of the layer to be transferred, and the quality of that layer. The following processes for forming a single crystalline substrate with a fragile layer inside the substrate are known in the prior art:                (1) use of a buried porous silicon layer as a fragile layer (T. Yonehara, “ELTRAN SOI-Epi Wafer and SCLIPS by Epitaxial Layer Transfer from Porous Si,” 2nd Int. Conf. Porous Semiconductors Science and Technology, p. 14, 2000) and its modifications where the fragile layer comprises porous silicon        (2) fragilization by ion implanted gaseous species (Smart-Cut™, described by Bruel in U.S. Pat. No. 5,374,564) and its modifications        (3) fragilization by hydrogen trapping onto buried defect layer (Usenko, U.S. Pat. No. 6,352,909, Matsui U.S. Pat. No. 6,191,007, see 21st preferred embodiment in the Matsui's patent).        
In the ELTRAN (N. Sato, K. Sakaguchi, K. Yamagata, T. Atoji, Y. Fujiyama, J. Nakayama, T. Yonehara, “High-quality epitaxial layer transfer (ELTRAN) by bond and etch-back of porous Si”, IEEE International SOI Conference, 1995, Tucson, Ariz., USA, pp. 176–177), an epitaxial layer is grown on top of the preformed porous silicon layer. The growing epilayer tends to seal the pores thus making the layer transfer possible. After some thickness achieved, the pores disappear, and quality of the further growing epitaxial layer gradually increases with thickness. A continuous single crystalline layer now covers a porous (i.e., fragile) layer. This puts a limit on a minimum thickness of the transferred layer. A typical (inherent) thickness of a transferred layer exceeds micron. For mainstream CMOS SOI manufacturing this thickness is too big. The transferred layer is further thinned back to about 0.2 micron thus also removing the worst quality part of the silicon cap, and leaving the best quality part of the silicon cap. Further thinning is limited because it increases thickness nonuniformity of the cap layer. Therefore, with the porous silicon based SOI processes it is difficult to form an SOI wafer with a thin cap layer. ELTRAN therefore is herd to use for next generations of integrated circuits that require starting SOI with thinner layers of 0.1 micron and less.
In the Smart-Cut™, the fragile layer is formed by hydrogen ion implantation at high dose (˜5×1016 cm−2) and low dose rate (less than 1013 cm−2s−1). The depth to which hydrogen ions penetrate into silicon determines an inherent thickness of the transferred layer. Hydrogen ions have smaller atomic mass than any other ions and therefore penetrate deeper than other ions. For typical ion implantation energies 30–100 keV the depth will be 0.3 to 1 micrometer. Implantation at lower ion energies for the Smart-Cut raises several problems. When the high-energy ion reaches a target (i.e., silicon), it dissipates its energy mostly because of interaction with the electronic subsystem of the silicon crystal. The energy of the penetrating ion gradually decreases as its energy is transferred mostly to electrons in the target material. When the ion energy drops to about 10 keV, the ion produces mostly atomic displacements, and it quickly stops, resulting in so-called end-of-the-range defects (i.e., silicon atoms displaced from their regular lattice positions). The change of the energy dissipation mechanism from electron to atomic displacements has an important consequence, whereby the implanted crystal contains a layer on its top that is very lightly damaged, a buried layer around projection range depth of the implanted ions that is heavily damaged, and an almost undamaged crystal bulk underneath of the projection range depth. In the Smart-cut, the use of the high-energy hydrogen ions allows to form a buried damaged and hydrogen rich layer under a layer of crystalline silicon that is very lightly damaged. Ion implantation at low energy (˜10 keV and less) makes effective atomic displacements right from point where ion reaches the target (i.e., from surface). It results in a damaged layer that is not buried under surface but it is located right on the surface. The damaged surface has an increased roughness and it cannot be bonded to another (handle) substrate. Therefore attempts to use low energy hydrogen implantation in Smart-cut resulted in layer transfer faults (C. Qian, B. Terreault, “Layer splitting by H-ion implantation in silicon: Lower limit on layer thickness?”, Materials Res. Soc. Symp.—Proceedings, Vol. 585, pp. 177–182, (2000). Finally, the hydrogen implantation based fragilization process is not suitable for thin cap SOI wafer manufacturing.
The most advanced thin layer transfer process known from the prior art is based on diffusion of hydrogen into silicon and collecting of the hydrogen at preformed buried layer of defects. This process can be used to fabricate SOI with extremely thin cap layers down to 30 nm in thickness or less (A. Usenko, W. N. Carr, Bo Chen, Y. Chabal, “Alternative smart-cut-like process for ultra-thin SOI fabrication” Advanced Semiconductor Manufacturing 2002 IEEE/SEMI Conference and Workshop, Boston, Mass., 2002 pp. 6–9). Hydrogen is delivered to the buried layer with either electrolytic means (Usenko, U.S. Pat. No. 6,352,909), or from hydrogen plasma (Usenko, U.S. Pat. No. 6,352,909, Matsui U.S. Pat. No. 6,191,007, see 21st preferred embodiment). The buried defect layer serves as an infinite capacity trap for the hydrogen.
However, the hydrogenation process takes considerably long time (˜1 hour in the methods known from the prior art). This increases the cost of manufacturing. The art would therefore benefit from an improved method for SOI fabrication. Such a method would incorporate steps of fast hydrogenation to avoid the drawbacks of the prior art.